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Data Sheet No. PD94713
IR3637SPBF
1% ACCURATE SYNCHRONOUS PWM CONTROLLER FEATURES
0.8V Reference Voltage Operates with a single 5V Supply Voltage Internal 400kHz Oscillator Soft-Start Function Fixed Frequency Voltage Mode Short Circuit Protection
DESCRIPTION
The IR3637 controller IC is designed to provide a simple synchronous Buck regulator for on-board DC to DC applications in a small 8-pin SOIC. The output voltage can be precisely regulated using the internal 0.8V reference voltage for low voltage applications. The IR3637 operates at a fixed internal 400kHz switching frequency to reduce the component size. The device features under-voltage lockout for both input supplies, an external programmable soft-start function as well as output under-voltage detection that latches off the device when an output short is detected.
APPLICATIONS
Computer Peripheral Voltage Regulator Memory Power supplies Graphics Card Low cost on-board DC to DC
TYPICAL APPLICATION
12V C3 5V C2 C1
Vc
Vcc HDrv Q1
D1
L1 Vout Q2 C6
SS/SD C4
IR3637 LDrv
Comp Fb Gnd R1
C5
R3
R2
Figure 1 - Typical application of IR3637.
ORDERING INFORMATION
PKG DESIG S S PACKAGE PIN PARTS PARTS T&R DESCRIPTION COUNT PER TUBE PER REEL Oriantation IR3637SPBF 8 95 -----Fig A IR3637STRPBF 8 ------2500
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IR3637SPBF
ABSOLUTE MAXIMUM RATINGS
Vcc Supply Voltage ................................................ Vc Supply Voltage .................................................. Storage Temperature Range ..................................... Operating Junction Temperature Range ..................... ESD Classification ................................................. Moisture Sensitivity Level ........................................ 16V 25V -65C To 150C 0C To 125C HMB Class 2 (2KV) JEDEC Standard JEDEC Level 1 @ 260C
Caution: Stresses above those listed in "Absolute Maximum Rating" may cause permanent damage to the device. These are stress
ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to "Absolute Maximum Rating" conditions for extended periods may affect device reliability
PACKAGE INFORMATION
Fb 1 Vcc 2 LDrv 3 Gnd 4
8 SS/SD 7 Comp 6 Vc 5 HDrv
Recommended Operating Conditions Parameter Vcc Vc Min 4.5 8 Max 5.5 14 Units V V
JA=154C/W JC=41.2C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over Vcc=5V, Vc=12V and 0CVFB
TEST CONDITION 25CMIN 0.792 0.789
TYP 0.800 0.800
MAX 0.808 0.811 0.1
UNITS V V % V V V V V mA mA mA mA A V
Fb Voltage Line Regulation UVLO UVLO Threshold - Vcc UVLO Hysteresis - Vcc UVLO Threshold - Vc UVLO Hysteresis - Vc UVLO Threshold - Fb Supply Current Vcc Dynamic Supply Current Vc Dynamic Supply Current Vcc Static Supply Current Vc Static Supply Current Soft-Start Section Charge Current Shutdown Threshold
LREG UVLO Vcc UVLO Vc UVLO Fb Dyn Icc Dyn Ic ICCQ ICQ SSIB SD
4.0 3.1 0.3 4 6 1 0.5 -15
4.2 0.25 3.3 0.2 0.4 8 15 3.3 1 -25
4.4 3.5 0.5 16 20 6 4.7 -35 0.4
Note1: Guaranteed by design. Not production tested.
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PARAMETER Error Amp Fb Voltage Input Bias Current Fb Voltage Input Bias Current Transconductance Oscillator Frequency Ramp-Amplitude Voltage Output Drivers Rise Time, Hdrv, Ldrv Fall Time,Hdrv, Ldrv Dead Band Time Max Duty Cycle Min Duty Cycle SYM
IFB1 IFB2
TEST CONDITION SS=3V, Fb=0.6V SS=0V, Fb=0.6V
MIN
TYP -0.1 -64 600 400 1.25
MAX
UNITS A A mho kHz V
gm
Freq VRAMP Tr Tf TDB TON TOFF
450 360
800 440
CL=1500pF, Vcc=12V,2V to 9V CL=1500pF, Vcc=12V, 9V to 2V Vcc=12V, 2V to 2V Fb=0.6V, Freq=400kHz Fb=1V
40 81
30 30 150 85
60 60 200 0
ns ns ns % %
PIN DESCRIPTIONS
PIN# 1 PIN SYMBOL PIN DESCRIPTION This pin is connected directly to the output of the switching regulator via resistor divider to Fb set the output voltage and provide feedback to the error amplifier. Vcc This pin provides biasing for the internal blocks of the IC as well as powers the low side driver. A minimum of 0.1F, high frequency capacitor must be connected from this pin to ground to provide peak drive current capability. Output driver for the synchronous power MOSFET. IC's ground pin. This pin must be connected directly to the ground plane. A high frequency capacitor (0.1 to 1F) must be connected from Vcc and Vc pins to this pin for noise free operation. Output driver for the high side power MOSFET. The negative voltage at this pin may cause instability for the gate drive circuit. To prevent this, a low forward voltage drop diode (e.g. BAT54 or 1N4148) is required between this pin and ground. This pin is connected to a voltage that must be at least 4V higher than the bus voltage (assuming 5V threshold MOSFET) and powers the high side output driver. A minimum of 0.1F, high frequency capacitor must be connected from this pin to ground to provide peak drive current capability. Compensation pin of the error amplifier. An external resistor and capacitor network is typically connected from this pin to ground to provide loop compensation. This pin provides user programmable soft-start function. Connect an extrnal capacitor from this pin to ground to set the start up time of the output. The converter can be shutdown by pulling this pin below 0.4V. During shutdown the upper FET is turned off and the lower FET is turned on.
2
3 4
LDrv Gnd
5
HDrv
6
Vc
7
Comp
8
SS / SD
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IR3637SPBF
BLOCK DIAGRAM
Vcc Bias Generator 3V 0.8V POR
4.2V 3V Vc 25uA 3.3V SS/SD 8 POR 0.8V Error Comp 25K 25K 0.4V Comp 7 POR FbLo Comp Error Amp R Reset Dom Q 64uA Max Ct Oscillator S
6 Vc 5 HDrv
2 Vcc 3 LDrv
Fb 1
4 Gnd
Figure 2 - Simplified block diagram of the IR3637.
THEORY OF OPERATION
Introduction The IR3637 is a fixed frequency, voltage mode synchronous controller and consists of a precision reference voltage, an error amplifier, an internal oscillator, a PWM comparator, 0.5A peak gate driver, soft-start and shutdown circuits (see Block Diagram). The output voltage of the synchronous converter is set and controlled by the output of the error amplifier; this is the amplified error signal from the sensed output voltage and the reference voltage. This voltage is compared to a fixed frequency linear sawtooth ramp and generates fixed frequency pulses of variable duty-cycle, which drives the two N-channel external MOSFETs.The timing of the IC is provided through an internal oscillator circuit which uses on-chip capacitor to set the oscillation frequency to 400kHz. Short-Circuit Protection The output is protected against the short-circuit. The IR3637 protects the circuit for shorted output by sensing the output voltage (through the external resistor divider). The IR3637 shuts down the PWM signals, when the output voltage drops below 0.4V. Under-Voltage Lockout The under-voltage lockout circuit assures that the MOSFET driver outputs remain in the off state whenever the supply voltage drops below set parameters. Lockout occurs if Vc or Vcc fall below 3.3V and 4.2V respectively. Normal operation resumes once Vc and Vcc rise above the set values. Shutdown The converter can be shutdown by pulling the soft-start pin below 0.4V. This can be easily done by using an external small signal transistor. During shutdown the control MOSFET driver is turned off and the synchronous MOSFET driver is turned on.
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THEORY OF OPERATION
Soft-Start The IR3637 has a programmable soft-start to control the output voltage rise and limit the current surge at the startup. To ensure correct start-up, the soft-start sequence initiates when the Vc and Vcc rise above their threshold (3.3V and 4.2V respectively) and generates the Power On Reset (POR) signal. Soft-start function operates by sourcing an internal current to charge an external capacitor to about 3V. Initially, the soft-start function clamps the E/A's output of the PWM converter and disables the short circuit protection. During the power up, the output starts at zero and voltage at Fb is below 0.4V. The feedback UVLO is disabled during this time by injecting a current (64A) into the Fb. This generates a voltage about 1.6V (64Ax25K) across the negative input of E/ A and positive input of the feedback UVLO comparator (see Figure 3). The magnitude of this current is inversely proportional to the voltage at soft-start pin. The 20A current source starts to charge up the external capacitor. In the mean time, the soft-start voltage ramps up, the current flowing into Fb pin starts to decrease linearly and so does the voltage at the positive pin of feedback UVLO comparator and the voltage negative input of E/A. When the soft-start capacitor is around 1V, the current flowing into the Fb pin is approximately 32A. The voltage at the positive input of the E/A is approximately: 32Ax25K = 0.8V The E/A will start to operate and the output voltage starts to increase. As the soft-start capacitor voltage continues to go up, the current flowing into the Fb pin will keep decreasing. Because the voltage at pin of E/A is regulated to reference voltage 0.8V, the voltage at the Fb is: VFB = 0.8-25Kx(Injected Current) The feedback voltage increases linearly as the injecting current goes down. The injecting current drops to zero when soft-start voltage is around 2V and the output voltage goes into steady state. As shown in Figure 4, the positive pin of feedback UVLO comparator is always higher than 0.4V, therefore, feedback UVLO is not functional during soft-start.
25uA SS/SD 3V
64uA Max
HDrv
POR Comp 0.8V 25K Error Amp LDrv
25K Fb 0.4V 64uAx25K=1.6V When SS=0
Feeback UVLO Comp
POR
Figure 3 - Soft-start circuit for IR3637. The output start-up time is the time period when softstart capacitor voltage increases from 1V to 2V. The startup time will be dependent on the size of the external soft-start capacitor. The start-up time can be estimated by: 25AxTSTART/CSS = 2V-1V For a given start up time, the soft-start capacitor can be estimated as: CSS 25AxTSTART/1V
Output of UVLO POR
3V
2V
Soft-Start Voltage Current flowing into Fb pin
1V
0V 64uA 0uA
Voltage at negative input 1.6V of Error Amp and Feedback UVLO comparator
0.8V 0.8V
Voltage at Fb pin
0V
Figure 4 - Theoretical operational waveforms during soft-start.
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IR3637SPBF
APPLICATION INFORMATION
Design Example: The following example is a typical application for IR3637. Appliaction circuit is shown in page 12. VIN = Vcc = 5V Vc=12V VOUT = 1.8V IOUT = 6A VOUT = 50mV FS = 400kHz Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The Fb pin is the inverting input of the error amplifier, which is internally referenced to 0.8V. The divider is ratioed to provide 0.8V at the Fb pin when the output is at its desired value. The output voltage is defined by using the following equation: VOUT = VREF x Css 25xtSTART (F) ---(2)
Where tSTART is the desired start-up time (ms) For a start-up time of 4ms, the soft-start capacitor will be 0.1F. Choose a ceramic capacitor at 0.1F. Boost Supply for Single 5V appliaction To drive the high side switch, it is necessary to supply a gate voltage at least 4V grater than the bus voltage. This is achieved by using a charge pump configuration as shown in Figure 6. This method is simple and inexpensive. The operation of the circuit is as follows: when the lower MOSFET is turned on, the capacitor (C1) is pulled down to ground and charges, up to VBUS value, through the diode (D1). The bus voltage will be added to this voltage when upper MOSFET turns on in next cycle, and providing supply voltage (Vc) through diode (D2). Vc is approximately: Vc 2VBUS - (VD1 + VD2) Capacitors in the range of 0.1F and 1F are generally adequate for most applications. The diode must be a fast recovery device to minimize the amount of charge fed back from the charge pump capacitor into VBUS. The diodes need to be able to block the full power rail voltage, which is seen when the high side MOSFET is switched on. For low voltage application, schottky diodes can be used to minimize forward drop across the diodes at start up.
VBUS D1 C3 D2 Vc VBUS C2 C1 Q1 L
(1 + R6) R5
---(1)
When an external resistor divider is connected to the output as shown in Figure 5.
VOUT IR3637
Fb R5 R6
Figure 5 - Typical application of the IR3637 for programming the output voltage. Equation (1) can be rewritten as: R6 = R5 x
(
VOUT -1 VREF
)
IR3637
HDrv Q2
Choose R5 = 1K This will result to R6 = 1.25K If the high value feedback resistors are used, the input bias current of the Fb pin could cause a slight increase in output voltage. The output voltage set point can be more accurate by using precision resistor. Soft-Start Programming The soft-start timing can be programmed by selecting the soft-start capacitance value. The start-up time of the converter can be calculated by using:
Figure 6 - Charge pump circuit. Input Capacitor Selection The input filter capacitor should be based on how much ripple the supply can tolerate on the DC input line. The ripple current generated during the on time of upper MOSFET should be provided by input capacitor. The RMS value of this ripple is expressed by:
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IRMS = IOUT Dx(1-D) ---(3) Where: D is the Duty Cycle, D=VOUT/VIN. IRMS is the RMS value of the input capacitor current. IOUT is the output current for each channel. For IOUT=6A and D=0.36, the IRMS=2.8A For higher efficiency, low ESR capacitor is recommended. Two capacitors of Sanyo's TPB series PosCap with 150F, 6.3V, 40m ESR and 1.4A ripple current will meet the ripple current requirement. Inductor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. Low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of inductor value can be reduced to desired maximum ripple current in the inductor (i). The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for desired operating ripple current can be determined using the following relation: i VOUT 1 ; t = Dx ; D = t VIN fS VOUT L = (VIN - VOUT)x ---(5) VINxixfS Where: VIN = Maximum Input Voltage VOUT = Output Voltage i = Inductor Ripple Current fS = Switching Frequency t = Turn On Time D = Duty Cycle VIN - VOUT = Lx If i = 40%(IO), then the output inductor will be: L = 1.2H The Coilcraft DO3316 series provides a range of inductors in different values, low profile suitable for large currents, 1.5H, 8A(Isat) is a good choice for this application. Output Capacitor Selection The criteria to select the output capacitor is normally based on the value of the Effective Series Resistance (ESR). In general, the output capacitor must have low enough ESR to meet output ripple and load transient requirements, yet have high enough ESR to satisfy stability requirements.
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The ESR of the output capacitor is calculated by the following relationship: ESR VO IO ---(4)
Where: VO = Output Voltage Ripple IO = Inductor Ripple Current VO=50mV and IO=2.4A Results to ESR=20.8m The Sanyo TPB series, PosCap capacitor is a good choice. The 6TPB150M 150F, 6.3V has an ESR 40m. Selecting two of these capacitors in parallel, results to an ESR of 20m which achieves our low ESR goal. Power MOSFET Selection The IR3637 uses two N-Channel MOSFETs. The selections criteria to meet power transfer requirements is based on maximum drain-source voltage (VDSS), gatesource drive voltage (VGS), maximum output current, Onresistance RDS(on) and thermal management. The MOSFET must have a maximum operating voltage (VDSS) exceeding the maximum input voltage (VIN). The gate drive requirement is almost the same for both MOSFETs. Logic-level transistor can be used and caution should be taken with devices at very low VGS to prevent undesired turn-on of the complementary MOSFET, which results a shoot-through current. The total power dissipation for MOSFETs includes conduction and switching losses. For the Buck converter the average inductor current is equal to the DC load current. The conduction loss is defined as: PCOND (Upper Switch) = ILOAD x RDS(on) x D x PCOND (Lower Switch) = ILOAD x RDS(on) x (1 - D) x = RDS(ON) Temperature Dependency The RDS(ON) temperature dependency should be considered for the worst case operation. This is typically given in the MOSFET data sheet. Ensure that the conduction losses and switching losses do not exceed the package ratings or violate the overall thermal budget.
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IR3637SPBF
For this design, IRF8910 is a good choice. The device provides two N-MOSFETs in a compact SOIC 8-Pin package. The IRF8910 has the following data: VDSS = 20V ID = 10A RDS(onh) =18.3 @ VGS=4.5V (Lower FET) RDS(on) =13.4 @ VGS=10V (Upper FET) The total conduction losses will be:
PCON(TOTAL)=PCON(Upper Switch)+PCON(Lower Switch)
These values are taken under a certain condition test. For more detail please refer to the IRF8910 data sheet. By using equation (6), we can calculate the switching losses. PSW = 95mW Feedback Compensation The IR3637 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency and adequate phase margin (greater than 45 ). The output LC filter introduces a double pole, -40dB/ decade gain slope above its corner resonant frequency, and a total phase lag of 180 (see Figure 8). The Resonant frequency of the LC filter expressed as follows: FLC = 1 2x LOxCO ---(7)
= 1.4 according to the IRF8910 data sheet for 150 C junction temperature PCON(TOTAL) =0.83W The switching loss is more difficult to calculate, even though the switching transition is well understood. The reason is the effect of the parasitic components and switching times during the switching procedures such as turn-on / turnoff delays and rise and fall times. The control MOSFET contributes to the majority of the switching losses in synchronous Buck converter. The synchronous MOSFET turns on under zero voltage conditions, therefore, the turn on losses for synchronous MOSFET can be neglected. With a linear approximation, the total switching loss can be expressed as: VDS(OFF) tr + tf x ILOAD x PSW = ---(6) T 2 Where: VDS(OFF) = Drain to Source Voltage at off time tr = Rise Time tf = Fall Time T = Switching Period ILOAD = Load Current The switching time waveform is shown in figure 7.
Figure 8 shows gain and phase of the LC filter. Since we already have 180 phase shift just from the output filter, the system risks being unstable.
Gain 0dB -40dB/decade Phase 0
FLC Frequency
-180
FLC
Frequency
Figure 8 - Gain and phase of LC filter. The IIR3637's error amplifier is a differential-input transconductance amplifier. The output is available for DC gain control or AC phase compensation. The E/A can be compensated with or without the use of local feedback. When operated without local feedback the transconductance properties of the E/A become evident and can be used to cancel one of the output filter poles. This will be accomplished with a series RC circuit from Comp pin to ground as shown in Figure 9.
VDS 90%
10% VGS td(ON) tr td(OFF) tf
Figure 7 - Switching time waveforms. From IRF8910 data sheet:
tr = 10ns tf = 4.1ns
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IR3637SPBF
Note that this method requires that the output capacitor should have enough ESR to satisfy stability requirements. In general the output capacitor's ESR generates a zero typically at 5kHz to 50kHz which is essential for an acceptable phase margin. The ESR zero of the output capacitor expressed as follows: 1 FESR = ---(8) 2 x ESR x Co
VOUT R6 Fb R5 VREF
Gain(dB)
Where: VIN = Maximum Input Voltage VOSC = Oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R5 and R6 = Resistor Dividers for Output Voltage Programming gm = Error Amplifier Transconductance For: VIN = 5.5V VOSC = 1.25V Fo = 40kHz FESR = 26.5kHz FLC = 7.50kHz R5 = 1K R6 = 1.25K gm = 600mho This results to R4=16.06K. Choose R4=16K To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole:
E/A
Comp Ve C9 R4 CPOLE
H(s) dB
FZ
Frequency
FZ 75%FLC FZ 0.75 x For: Lo = 1.5H Co = 300F FZ = 5.6kHz R4 = 16K Using equations (11) and (13) to calculate C9, we get: 1 2 LO x CO ---(13)
Figure 9 - Compensation network without local feedback and its asymptotic gain plot. The transfer function (Ve / VOUT) is given by: H(s) = gm x
(
R5 R6 + R5
sR4C9 ) x 1 +sC9
---(9)
The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: R5 |H(s)| = gmx x R4 ---(10) R6xR5 FZ = 1 2xR4xC9 ---(11)
C9 = 1.77nF Choose C9 = 1.8nF One more capacitor is sometimes added in parallel with C9 and R4. This introduces one more pole which is mainly used to supress the switching noise. The additional pole is given by: 1 FP = C9 x CPOLE 2 x R4 x C9 + CPOLE The pole sets to one half of switching frequency which results in the capacitor CPOLE: CPOLE = 1 xR4xfS - 1 C9 fS for FP << 2 1 xR4xfS
The gain is determined by the voltage divider and E/A's transconductance gain. First select the desired zero-crossover frequency (Fo): Fo > FESR and FO (1/5 ~ 1/10)x fS Use the following equation to calculate R4: R4 = 1 VOSC FoxFESR R5 + R6 x x x gm VIN FLC2 R5 ---(12)
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For a general solution for unconditionally stability for any type of output capacitors, in a wide range of ESR values we should implement local feedback with a compensation network. The typically used compensation network for voltage-mode controller is shown in Figure 10.
ZIN C10 R8 R6 Fb R5
Gain(dB)
FP1 = 0 FP2 = FP3 = 1 2xR8xC10 1 C12xC11 2xR7x C12+C11 1 2xR7xC11
VOUT R7
C12 C11 Zf
(
)
1 2xR7xC12
FZ1 =
1 1 FZ2 = 2xC10x(R6 + R8) 2xC10xR6 Cross Over Frequency: VIN 1 FO = R7xC10x x VOSC 2xLoxCo Where: VIN = Maximum Input Voltage VOSC = Oscillator Ramp Voltage Lo = Output Inductor Co = Total Output Capacitors
E/A
Comp
Ve
VREF
---(15)
H(s) dB
FZ1
FZ2
FP2
FP3
Frequency
Figure 10 - Compensation network with local feedback and its asymptotic gain plot. In such configuration, the transfer function is given by: 1 - gmZf Ve = VOUT 1 + gmZIN The error amplifier gain is independent of the transconductance under the following condition:
The stability requirement will be satisfied by placing the poles and zeros of the compensation network according to following design rules. The consideration has been taken to satisfy condition (14) regarding transconductance error amplifier. 1) Select the crossover frequency: Fo < FESR and Fo (1/10 ~ 1/6)x fS 2) Select R7, so that R7 >> 2
gmZf >> 1
and
gmZIN >>1
gm
---(14)
By replacing ZIN and Zf according to Figure 7, the transformer function can be expressed as: H(s)= 1 x sR6(C12+C11)
[
(1+sR7C11)x[1+sC10(R6+R8)] C12xC11 1+sR7 x(1+sR8C10) C12+C11
3) Place first zero before LC's resonant frequency pole. FZ1 75% FLC 1 C11 = 2 x FZ1 x R7 4) Place third pole at the half of the switching frequency. fS FP3 = 2 1 C12 = 2 x R7 x FP3 C12 > 50pF If not, change R7 selection. 5) Place R7 in (15) and calculate C10:
(
)]
As known, transconductance amplifier has high impedance (current source) output, therefore, consider should be taken when loading the E/A output. It may exceed its source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the necessary range. The compensation network has three poles and two zeros and they are expressed as follows:
C10
VOSC 2 x Lo x Fo x Co x VIN R7
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6) Place second pole at the ESR zero. FP2 = FESR 1 R8 = 2 x C10 x FP2 Check if R8 > 1 Layout Consideration The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, make all the connection in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to reduce the ESR replace the single input capacitor with two parallel units. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. In multilayer PCB use one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point.
gm
If R8 is too small, increase R7 and start from step 2. 7) Place second zero around the resonant frequency. FZ2 = FLC 1 R6 = - R8 2 x C10 x FZ2 8) Use equation (1) to calculate R5. VREF R5 = x R6 VOUT - VREF These design rules will give a crossover frequency approximately one-tenth of the switching frequency. The higher the band width, the potentially faster the load transient speed. The gain margin will be large enough to provide high DC-regulation accuracy (typically -5dB to 12dB). The phase margin should be greater than 45 for overall stability. Based on the frequency of the zero generated by ESR versus crossover frequency, the compensation type can be different. The table below shows the compensation type and location of crossover frequency. Compensator Location of Zero Typical Type Crossover Frequency Output (FO) Capacitor Type II (PI) FLC < FESR < FO < fS/2 Electrolytic, Tantalum Type III (PID) FLC < FO < FESR < fS/2 Tantalum, Method A Ceramic Type III (PID) FLC < FO < fS/2 < FESR Ceramic Method B Table - The compensation type and location of zero crossover frequency. Detail information is dicussed in application Note AN1043 which can be downloaded from the IR Web-Site. All design should be tested for stability to verify the calculated values.
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IR3637SPBF
TYPICAL APPLICATION
Two Supplies Application: Vc=12V, Vin=Vcc=5V to 1.8V @ 6A
VIN 5V Gnd 12V
C1 150uF
C2 150uF
C4 1uF
C5 1uF Q1 IRF8910
Vcc
C3 1uF
Vc HDrv
D1
L1 1.5uH DO3316P-152
SS/SD
C6 0.1uF
U1 IR3637
LDrv
VOUT 1.8V @ 6A
C7 150uF C10 C8 150uF 1uF
Comp Gnd
C9 1.8nF C11 47pF R4 16K
Gnd
Fb
R5 1K
R6 1.24K
Figure 11 - Typical Application for IR3637.
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IR3637SPBF TYPICAL APPLICATION
Single 5V Application
5V D1
C3
C4
C5 C1
Vcc
Vc HDrv Q1
D2
L1 Vout Q2 C7
SS/SD C8
U1
LDrv
IR3637
Comp
R6 Fb Gnd R5
C9 R4
Figure 12 - Typical application for single 5V
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IR3637SPBF TYPICAL APPLICATION
Two Supplies Application, Vcc=Vc=12V, Vin=5V
12V
5V
C3
C4 C1 Vcc Vc HDrv Q1
D2
L1 Vout Q2 C7
C8
SS/SD U1
IR3637
Comp
LDrv
R6 Fb Gnd R5
C9 R4
Figure 13 - Typical application using 12V for biasing both Vcc and Vc and 5V for Bus Voltage
For proper start up the 5V rail needs to start before 12V
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IR3637SPBF TYPICAL OPERATING CHARACTERISTICS
800.50
Vfb vs. Temperature
Soft Start Charge Current -19
800.00
-20
799.50
-21 -22 uA
799.00
-23 -24
798.50
-25
798.00
-26 -27
797.50 0 20 40 60 80 100 120 140
0
25
50 Temp, C
75
100
125
E/A's Transconductance
Static Vcc Current 4.5
0.62
4.25
0.6 0.58 mmhos
4 3.75 mA
0 25 50 Temp, C 75 100 125
0.56 0.54
3.5 3.25 3
0.52
2.75
0.5
2.5 0 25 50 Temp, C 75 100 125
Static Vc Current 4.25 4 3.75 3.5 mA
mA 6.75 6.5 6.25 6 5.75 7
Dynamic Vcc Current
3.25 3 2.75 2.5 2.25 2 0 25 50 Temp, C 75 100 125
5.5 0 25 50 Temp, C 75 100 125
Rev. 1.1 06/16/05
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15
IR3637SPBF TYPICAL OPERATING CHARACTERISTICS
Dynamic Vc Current 12.75
36 Rise Time-HDrv
12.5
31
12.25 mA
ns
26
12
21
11.75
16
11.5 0 25 50 Temp, C 75 100 125
11 0 25 50 Temp, C 75 100 125
Fall Time-HDrv 41 36 26 31 ns ns 26 21 16 16 11 0 25 50 Temp, C 75 100 125 11 0 25 21 31
Rise Time-LDrv
Smoothed
50
75
100
125
Temp, C
Fall Time-HDrv 31
26
ns
21
Smoothed
16
11 0 25 50 75 100 125 Temp, C
16
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Rev.1.1 06/16/05
IR3637SPBF TYPICAL PERFORMANCE CURVES
Test Conditions: Vcc=Vin=5V, Vc=12V, Vout=1.8V, Iout=0-7A, Ta=Room Temp, No Air Flow. Unless otherwise specified.
Figure 14 - Start up waveforms Ch1: Vin=Vcc, Ch2: Vc, Ch3: Vss, Ch4: Vout
Figure 15 - Start up waveforms Ch1: Vin=Vcc, Ch3: Vss, Ch4: Vout
Figure 16 - Gates waveforms Ch1: Hdrv, Ch2: Ldrv, Ch4: Inductor Current ILoad=5A
Figure 17 - Gates waveforms Ch1: Hdrv, Ch2: Ldrv, Ch3: Inductor Point ILoad=5A
Rev. 1.1 06/16/05
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17
IR3637SPBF TYPICAL OPERATING WAVEFORMS
Test Conditions: Vcc=Vin=5V, Vc=12V, Vout=1.8V, Iout=0-7A, Ta=Room Temp, No Air Flow. Unless otherwise specified.
Figure 18 - Shutdown by shorting the SS pin Ch1: Hdrv, Ch2: Ldrv, Ch3:SS ILoad=5A
Figure 19 - Output Voltage Ripple Ch1: Vout, Ch4: Inductor Current ILoad=5A
Figure 20 - Load Transient (0-5A) Ch1: Vout, Ch4: Step Load Current
Figure 21 - Load Transient (5-0A) Ch1: Vout, Ch4: Step Load Current
18
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Rev.1.1 06/16/05
IR3637SPBF TYPICAL PERFORMANCE CURVES
Test Conditions: Vcc=Vin=5V, Vc=12V, Vout=1.8V, Iout=0-8A, Ta=Room Temp, No Air Flow. Unless otherwise specified.
E fficien cy V c=12V , V cc= V b u s= 5V , Io u t=0-8A, F s=40 0kHz
100 90 80 70 Efficiency (%) 60 50 40 30 20 10 0 0 2 4 Io u t (A ) 6 8 10
Figure 22 - Efficiency using IRF8910 Dual MOSFET
Rev. 1.1 06/16/05
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19
IR3637SPBF
(S) SOIC Package 8-Pin Surface Mount, Narrow Body
H A B C
E
DETAIL-A PIN NO. 1 D 0.380.015 x 45 TF K
L DETAIL-A I J
G
8-PIN SYMBOL A B C D E F G H I J K L T MAX MIN 4.98 4.80 1.27 BSC 0.53 REF 0.46 0.36 3.99 3.81 1.72 1.52 0.25 0.10 7 BSC 0.19 5.80 0 0.41 1.37 0.25 6.20 8 1.27 1.57
NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.
20
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Rev.1.1 06/16/05

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